An integrated circuit (IC) is an interconnected network of microcircuits which form discrete IC devices. A microelectronic die comprises a die substrate upon which microcircuits are formed. The die substrates are diced from semiconductor material, examples of which include, among others, wafers of silicon (Si), gallium arsenide (GaAs), Indium Phosphate (InP) and their derivations. Various techniques are used, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic IC devices in the form of transistors, resistors, and others on the wafer. The IC devices are interconnected within individual dice to define a specific electronic circuit that performs a specific function, such as the function of a microprocessor or a computer memory.
Optical micro-lithography is a process used to produce ultra-high resolution features on the wafer. In one aspect of the process, radiation in the deep ultraviolet (DUV) wavelengths produced by a laser and imaged though optics and slit reticles provides the illumination source that projects through the openings of a lithographic mask upon the surface of the wafer. The micro-lithography systems must overcome a multitude of challenges to produce an illumination that is suitable for resolving 150 nm features and below.
One type of optical micro-lithographic system is known as step and scan (S&S). The basic subsystems of the S&S system comprises a laser subsystem to provide the radiation, beam focusing and scanning subsystem that shapes and guides the radiation, and the wafer subsystem in which the wafer is processed.
The challenges of providing error-free illumination can be addressed at the subsystem level. The laser must provide radiation at a predefined wavelength and uniformity of power. Illumination errors develop if the wavelength and/or power were to drift from nominal.
The beam focusing and scanning subsystem must carry, process and steer the radiation to illuminate predetermined areas of the wafer. This subsystem comprises lenses, filters, mirrors, and positioning mechanisms. Errors occur at the lenses due to issues of alignment, astigmatism, as well as compaction and absorption which can vary over time. Filters have similar error potential as the lenses. The mirrors have issues related to alignment and flatness.
The wafer subsystem must be able to carry and support the wafer during scanning (the wafer stage) as well as provide the final component of illumination control (the reticle stage). At the wafer stage, errors are introduced due to wafer handling, including issues related to the wafer chuck flatness, alignment, conveyance, positioning, and control systems. The positioning mechanisms have issues related to mechanical devices, such as alignment, wear, inertia, and vibration. The control systems must provide suitable algorithms for numerical control of the positioning actuators, with feedback control for dynamic correction. At the reticle stage, the illumination is shaped by passing the radiation through an illumination slit to illuminate the desired scan field. Errors related to reticle issues include accuracy of manufacture, alignment, and wear.
Step and scan refers to the process in which the wafer is illuminated. The reticle comprises a rectangular slit that projects a rectangular exposure onto the wafer surface. The rectangular exposure is scanned across the surface of the wafer in multiple, predefined fields. The scanned field is also a rectangular. Issues related to the quality of the illumination at the surface of the wafer are compounded by all the potential error issues of the individual subsystems, which can produce a scanned field that has issues of static and dynamic distortion, image plane deviations, and overlay.
Another important factor related to potential errors in the S&S system include wafer quality. At the resolutions of interest, wafer planarity is a crucial factor in illumination focus. Control for real-time focusing is required to follow the terrain of the wafer. The focus is controlled by sampling a finite number of areas as the wafer is scanned. Servo controlled wafer stages adjust the position of the wafer to keep the wafer's surface at the optimum lithographic focal point. A compromise has to be made as only a finite number of samples are made which must be averaged over the scanned field.
Additional sources of focus error as a result of wafer quality include: vendor-specific wafer bevel and systematic non-parallelism; layer- and process-specific wafer thickness variation, such as interlayer dielectric (ILD) deposition and chemical and mechanical planarization (CMP) variations;.
Focus error can also be caused by focus sensors and focus software interacting with machine variables. Focus error can also be caused by the errors of conventional metrologies and monitors of focus and tilt, and in particular, where these errors are not the same during test and during production exposure.
These errors issues accumulate at the exposure location, and therefore the errors must be tightly budgeted. In order to minimize errors characteristic in S&S systems, the subsystems are held to the tightest of tolerance achievable, which dramatically increases the cost of the system. In-line defect monitoring is used but is limited by sampling rate and damage assessment/mitigation.
Methods are needed to control and adjust for the characteristic error issues inherent in the S&S system. As IC device resolution is made even smaller, negating these error issues become critical.